Development of hybrid wafer scale integrated circuits has been directed toward further reducing the size of the functional circuitry on a single substrate and providing interconnection capability in the circuitry that is compatible with propagation of high-speed signals. As a consequence of these requirments, conductor densities in large scale integrated (LSI) and hybrid circuits have reached a limit for single-layer topology, creating a need for practical methods useful in forming multi-layer circuits in which planes of interconnected conductive traces are built up on a substrate.
A multi-layer circuit comprises at least two layers of conductive traces, usually formed so that the primary signal propagation directions in adjacent layers are orthogonal to each other. In addition to the layers for conveying signals, the typical circuit of this type requires several additional layers for conveying power to the components comprising the circuit. Each layer of conductive traces is separated from its adjacent layers by a dielectric coating. Conductive traces for the second and successive layers are formed on the dielectric coating covering the preceding layer of conductive traces, with inter-layer connections between the conductive traces occurring at vias that extend transversely through the dielectric coating separating adjacent layers.
Overlaying a series of closely-spaced, parallel conductive traces applied to a substrate with an electrically insulating dielectric coating normally produces a washboard surface on which subsequent layers of circuitry must be formed, since the dielectric coating tends to follow the undulations of the surface to which it is applied as it flows over and between adjacent conductive traces. However, successful fabrication of high-density, multi-layer circuits requires a relatively planar underlying surface upon which to form the next layer of conductive traces. The conventional method for providing a smooth surface calls for applying four to five additional coats of dielectric material over each layer of conductive traces; yet, in most attempts, the resulting surface is not planar. Each successive dielectric coat formed using conventional materials and techniques tends to have a generally constant thickness, and thus conforms to the undulating surface of the previously formed circuit traces. Rather than filling in the low areas between conductive traces, each coat follows the surface contour of the preceding coat. It has been suggested that the wafer on which the multi-layer circuit is being formed can be mechanically polished to smooth out these undulations in the dielectric coating. However, due to the production of particulates and likely damage to the micro circuitry that usually results from such abrasive techniques, this approach is generally impractical.
Accordingly, there is a need for developing a method for producing a planar surface of a dielectric coating on which a conductive trace can be applied to form successive layers of a multi-layer circuit. The planar surface should be provided without applying many coats of dielectric material between each layer of conductive traces and without resorting to mechanical abrasion to smooth the surface.